This invention relates to a system for refreshing dynamic memories, and more particularly, to a system for refreshing a semiconductor memory by writing into memory locations whose row addresses are determined by a refresh counter, in a manner which expands the time the memory may operate without reserving a memory cycle for the refreshing operation.
Various techniques are used to refresh dynamic semiconductor memories to keep data from being lost as a result of the leakage of charge from memory cells over a period of time. Generally a refresh cycle is used to periodically restore the charge back to its initial value by operating on one row of memory at a time, or on groups of several rows which are a very small fraction of the total number of rows of the memory.
Typically all of the rows of a semiconductor memory must be refreshed in about two milliseconds before any row needs to be refreshed again. The addresses of the row being refreshed are accessed by a refresh cycle which contains a count that keeps track of the row that was the most recently refreshed. When the counter is incremented it refreshes the next row in the sequence of the refresh cycle. An example of a refresh counter for such a system is shown in U.S. Pat. No. 4,347,589 issued Aug. 31, 1982 to Robert J. Proebsting, which is entitled "Refresh Counter Test".
The memory cells of a dynamic metal oxide semiconductor memory (MOS) requires a significantly smaller area compared to a static MOS memory, which reduces the costs of implementing dynamic MOS memories. The operating power requirements of a dynamic MOS memory are also generally significantly lower, but very large scale dynamic semiconductor memories in the range of 512K to 2 M words still have significantly high enough power requirements that only a very small number of the rows of the memory may be refreshed at any given time, in order to conserve refresh power.
For example in a memory 8 banks of 256K words, there may be 128 rows. In order to keep power requirements to a reasonable level, the number of rows that are refreshed at any given time must be limited, for example one row of each of the 8 banks may be refreshed at a given time within reasonable power restrictions. However, with this relatively large number of rows, and the relatively few rows which may be refreshed at any given time, the potential increases for conflicting refresh and memory access requests by a requesting device.
In U.S. Pat. No. 4,376,988 issued Mar. 15, 1983, to Volker Ludwig, et al, entitled "Method and Circuitry Arrangement for Refreshing Data Stored in a Dynamic MOS Memory", a memory with 128 lines and 128 columns, which requires memory cell refreshing every two milliseconds, is disclosed. In this system, each line is refreshed after 15.6 microseconds. The refreshing process itself lasts approximately 450 nanoseconds. In the described memory of this patent, the longest memory cycle was a write process which lasted approximately 1.7 microseconds.
In order to obtain a refreshing cycle of 15.6 microseconds with the maximum possible write process delay, the refresh time was shortened to 12.5 microseconds. Large scale data processing systems using memories on the order of 256K words, advantageously use architecture which requires memory cycles that vary from normal operating cycle of 450 nanoseconds to up to 10 microseconds. With the system of the Ludwig, et al, patent, a refresh would have to occur every 2 or 3 microseconds to accommodate a memory cycle of 10 microseconds which would be impractically short for this type of architecture.
Two commonly used types of system for the refreshing of semiconductor memory systems are the "burst mode" and the "interleaved mode". In the burst mode all, or some major segment of the memory, is refreshed as required, and all accessing for reading or writing of the memory is temporarily interrupted. In the interleaved mode the control circuitry determines the times of operation when access to the memory is not available for either reading or writing. During such times the system will be free to refresh the memory cells. Thus an activated read or write will not be interrupted, but refresh cycles will be interleaved with the read and write cycles on a non-interfering basis.
Interleaving of refresh cycles, however, may not by itself provide sufficient access at times to the memory system to satisfy the refresh requirement interval for all memory cells. In such event, the reading and writing functions may have to be interrupted to complete the refresh of the entire memory system. The interleaving technique generally minimizes the time that is required by the system simply to refresh the memory. However, prior implementations of such a technique have often resulted in excessive circuit requirement to accommodate the "least recently used" criteria.
U.S. Pat. No. 4,357,686 issued Nov. 2, 1982 to James H. Scheuneman entitled "Hidden Memory Refresh" described a memory which employed a dedicated refresh flag memory, which has a flag bit associated with each row of the system memory array, and circuitry for writing into the memory for reading each refresh flag, and for refreshing only those rows that were not accessed during the operating period. An alternate embodiment was also described, in which a refresh operation was performed in an interleaved mode where high and low priority periods were established so that the refresh operation was either optional or mandatory in accordance with the priority, and depending on whether or not the memory was active. Both of these described embodiments of U.S. Pat. No. 4,357,686, however, required a refresh flag memory for each row of a memory array.
A memory refresh technique for refreshing a semiconductor memory is described in "FET Memory with Hidden Refresh" by A. R. Basilico and R. M. Dinkjian; IBM Technical Disclosure Bulletin Vol. 25, No. 7A December 1982. The resettable, single-direction up counter described in this article controls the minimum time between successive refresh operations by inhibiting refresh during the first eight counts of counter after a refresh, allows a refresh to occur during the next seven counts only if the memory is not busy, and dictates that a mandatory refresh shall occur at a count of fifteen, at which count the counter is full. The purpose of this technique was to establish the minimum refresh time during periods when the memory was not heavily used.
The present invention provides a system in which a large capacity semiconductor memory may be refreshed in a manner which maximizes the operating time of the memory between refresh cycles, and at the same time allows for variable read-write memory access times.